For copper-to-copper clearance rules we do something similar by creating a Net Class for DDR with sub-classes for Data banks 0 to 7 and Address/Control. After we place components we will update the timing rules for each sub-class. To properly use automation later or even make hand routing easier we need to create Constraint Classes were are timing/length matching rules will be defined along with differential pairs, topology, cross-talk, and other electrical rules.įor our DDR circuit we will create a DDR Constraint Class with sub-classes for Data banks 0 to 7 and Address\Control. As we work on designing the schematic we will create most our rules via the Constraint Editor System (CES) Figure 1. Even a basic PCB needs some kind of rules trace widths, copper to copper spacing, component spacing, etc. These are the backbone of creating a PCB design to achieve first pass success, meet electrical requirements, and produce a high quality product.
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